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1/48 january 2006 M69KB096AA 64 mbit (4m x16) 1.8v supply, 80mhz clock rate, burst psram features summary supply voltage ?v cc = 1.7 to 1.95v core supply voltage ?v ccq = 1.7 to 3.3v for i/o buffers asynchronous modes ? asynchronous random read: 70ns and 85ns access time ? asynchronous write ? asynchronous page read page size: 16 words subsequent read within page: 20ns synchronous burst read and write modes ? burst write in continuous mode ? burst read: fixed length (4, 8, or 16 words) or continuous mde maximum clock frequency: 66mhz, 80mhz burst initial latency: 50ns (4 clock cycles) at 80mhz output delay: 9ns at 80mhz byte control by lb /ub low power consumption ? asynchronous random read mode: < 25ma ? asynchronus page read mode (subsequent read operations): < 15ma ? synchronous burst read initial access: < 35ma continuous burst read: < 15ma ? standby current: 120a ? deep power-down current: 10a (typ) figure 1. package low power features ? temperature compensated refresh (tcr) ? partial array refresh (par) ? deep power-down (dpd) mode operating temperature ? ?30c to +85c the M69KB096AA is only available as part of a multi-chip package product wafer
M69KB096AA 2/48 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 upper byte enable (ub ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 lower byte enable (lb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 clock input (k). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 configuration register enable (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v ccq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 vss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v ssq ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 asynchronous random read and write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 asynchronous page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mixed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 partial array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 programming and reading the configuration re gisters using the cr controlled method . 13 programming and reading the configuration registers by the software method. . . . . . . . . 13 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operating mode bit (bcr15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 latency counter bits (bcr13-bcr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wait polarity bit (bcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wait configuration bit (bcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 clock configuration bit (bcr6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 driver strength bit (bcr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/48 M69KB096AA burst wrap bit (bcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 burst length bits (bcr2-bcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 page mode operation bit (rcr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 temperature compensated refresh bits (rcr6-rcr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 deep power-down bit (rcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 partial array refresh bits (rcr2-rcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
M69KB096AA 4/48 summary description the M69KB096AA is a 64 mbit (67,108,864 bit) psram, organized as 4,194,304 words by 16 bits. the memory array is implemented using a one transistor-per-cell topology, to achieve bigger ar- ray sizes. this device is a high-speed cmos, dynamic ran- dom-access memory. it provides a high-density solution for low-power handheld applications. the M69KB096AA includes the industry standard flash memory burst mode that dramatically in- creases read/write over that of other low-power sram or psrams. the psram interface supports both asynchro- nous and burst-mode transfers. page mode ac- cesses are also included as a bandwidth- enhancing extension to the asynchronous read protocol. psrams are based on the dram technology, but have a transparent internal self-refresh mecha- nism that requires no additional support from the system memory controller, and has no significant impact on the device read/write performance. the device has two configuration registers, acces- sible to the user to define the device operation: the bus configuration register (bcr) and the refresh configuration register (rcr). the bus configura- tion register (bcr) indicates how the device inter- acts with the system memory bus. overall, it is identical to its counterpart in burst-mode flash memory devices. the refresh configuration reg- ister (rcr) is used to control how the memory ar- ray refresh is performed. at power-up, these registers are automatically loaded with default set- tings and can be updated any time during normal operation. to minimize the value of the standby current dur- ing self-refresh operations, the M69KB096AA in- cludes three system-accessible mechanisms configured via the refresh configuration register (rcr): the temperature compensated refresh (tcr) is used to adjust the refresh rate according to the operating temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. the partial array refresh (par) performs a limited refresh of the part of the psram array that contains essential data. the deep power-down (dpd) mode completely halts the refresh operation. it is used when no essential data is being held in the device. figure 2. logic diagram table 1. signal names a0-a21 address inputs dq0-dq15 data inputs/outputs e chip enable input cr configuration register enable input g output enable input w write enable input ub upper byte enable input lb lower byte enable input k clock input l latch enable input wait wait output v cc core supply voltage v ccq input/output buffers supply voltage v ss ground v ssq input/output buffers ground ai10584b 22 a0-a21 w dq0-dq15 v cc M69KB096AA g 16 e ub lb v ss cr k l v ccq v ssq wait
5/48 M69KB096AA signal descriptions the signals are summarized in figure 2., logic di- agram , and table 1., signal names . address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing read and write operations. data inputs/outputs (dq8-dq15). the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. when disabled, the data in- puts/outputs are high impedance. data inputs/outputs (dq0-dq7). the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. chip enable (e ). chip enable, e , activates the device when driven low (asserted). when deas- serted ( v ih ), the device is disabled and goes auto- matically in low-power standby mode or deep power-down mode. output enable (g ). output enable, g , provides a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common i/o data bus. write enable (w ). write enable, w , controls the bus write operation of the memory. when assert- ed ( v il ), the device is in write mode and write op- erations can be performed either to the configuration registers or to the memory array. upper byte enable (ub ). the upper byte en- able, ub , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. lower byte enable (lb ). the lower byte en- able, lb , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. if both lb and ub are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as e remains low. clock input (k). the clock, k, is an input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read and write operations. the clock input is required during all synchronous operations, except in standby and deep power- down. it must be kept low during asynchronous operations. configuration register enable (cr). when this signal is driven high, v ih , write operations load ei- ther the value of the refresh configuration regis- ter (rcr) or the bus conf iguration register (bcr). latch enable (l ). the latch enable input is used to latch the address. once the first address has been latched, the state of l controls whether subsequent addresses come from the address lines (l = v il ) or from the internal burst counter (l = v ih ). the latch enable signal, l , must be held low, v il , during asynchronous operations. wait (wait). the wait output signal provides data-valid feedback during synchronous burst read and write operations. the signal is gated by e . driving e high while wait is asserted may cause data corruption. once a read or write operation has been initiated, the wait signal goes active to indicate that the M69KB096AA device requires additional time be- fore data can be transferred. the wait signal also is used for arbitration when a read or write operation is launched while an on- chip refresh is in progress (see figure 6., collision between refresh and read operation and figure 7., collision between refresh and write opera- tion ). the wait signal on the M69KB096AA device is typically connected to a shared system-level wait signal. the shared wait signal is used by the pro- cessor to coordinate transactions with multiple memories on the synchronous bus. see the operating modes section for details on the wait signal operation. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, write, etc.) and for driving the refresh logic, even when the device is not being accessed. v ccq supply voltage. v ccq provides the power supply for the i/o pins. this allows all outputs to be powered independently from the core power supply, v cc . v ss ground. the v ss ground is the reference for all voltage measurements. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ccq . v ssq must be connected to v ss .
M69KB096AA 6/48 figure 3. block diagram note: functional block diagram illustrates simplified device operation. ai08721c a21-a0 i/o buffers control logic 4,096k x 16 memory array e w g k l cr wait lb ub dq7-dq0 dq15-dq7 address decode logic refresh configuration register (rcr) bus configuration register (bcr)
7/48 M69KB096AA table 2. bus modes? asynchronous mode table 3. bus modes? synchronous burst mode note: 1. when lb and ub are in select mode (low), dq15-dq0 are affected. when only lb is in select mode, dq7-dq0 are affected. when only ub is in the select mode, dq15-dq8 are affected. 2. the wait polarity is configured throu gh the bus configuration register (bcr10). 3. the device consumes active power in this mode whenever addresses are changed. 4. when the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influenc e. 5. v in = v cc or 0v. 6. the device remains in deep power-down m ode until the rcr register is reconfigured. 7. the synchronous burst mode is initialized through the bus configuration register (bcr15). 8. the clock polarity is configured through the bus configuration register (bcr6). 9. the clock signal, k, must remain stable during burst suspend operations. mode power k l e g w cr lb , ub wait (2) dq15-dq0 (1) notes asynchronous read active > standby llllhl l 1 low z data-out 3 asynchronous write active > standby lllxll l 1 low z data-in 3 standby standby l x h x x l x high z high-z 4,5 write configuration register active l l l h l h x low z high-z deep power- down (dpd) deep power- down l x h x x x x high-z high-z 6 mode power k l e g w cr lb , ub wait (2) dq15-dq0 (1) notes initial burst read active > standby ! l l x h l l low z data-out 3, 7, 8 initial burst write active > standby ! l l h l l x low z data-in 3, 7, 8 subsequent burst operation active > standby ! hlxxx llow z data-in or data-out 3, 7, 8 burst suspend active > standby x (9) x l h x l x low z high-z 3, 7 write configuration register active ! l l h l h x low z high-z 7, 8 deep power- down (dpd) deep power- down l x h x x x x high-z high-z 6
M69KB096AA 8/48 operating modes the M69KB096AA supports asynchronous ran- dom read, page read and synchronous burst read and write modes. the device mode is defined by the value that has been loaded into the bus configuration register. the page mode is controlled by the refresh con- figuration register (rcr7). power-up psram devices include an on-chip voltage sen- sor used to launch the power-up sequence. v cc and v ccq must be applied simultaneously. once they reach a stable level, equal to or higher than 1.70v, the device will require t vchel to complete its self-initialization process. during the initializa- tion period, the e signal should remain high. once initialization has completed, the device is ready for normal operation. initialization will configure the bus configuration register (bcr) and the refresh configuration register (rcr) with their default settings (see table 5., page 16 , and table 9., refresh configuration register definition ). see figure 34., power-up ac waveforms and ta- ble 19., power-up ac characteristics , for details on the power-up timing. asynchronous random read and write modes at power-up, the device is in asynchronous ran- dom read mode. this mode uses the industry standard control bus (e , g , w , lb , ub ). read op- erations are initiated by bringing e , g , and lb , ub low, v il , while keeping w high, v ih . valid data will be gated through the output buffers after the spe- cific access time t avqv has elapsed. the wait signal will remain active until valid data is output from the device and its state should be ig- nored. write operations occur when e , w , lb and ub are driven low. during asynchronous random write operations, the g signal is ?don't care? and w will override g . the data to be written is latched on the rising edge of e , w , lb or ub (whichever occurs first). during write operations, the wait signal in- dicates to the system memory controller that data have been programmed into the memory. during asynchronous operations (page mode dis- abled), the l input can either be used to latch the address or kept low, v il, during the entire read/ write operation. the clock input signal k must be held low, v il . see figures 15 , 16 and table 15. for details of asynchronous read ac timing requirements. see figures 23 , 24 , 25 , 26 , and table 17. for de- tails of asynchronous write ac timing require- ments. asynchronous page read mode the asynchronous page read mode gives greater performance, even than the traditional asynchro- nous random read mode. the page mode is not available for write operations. asynchronous page read mode is enabled by setting rcr7 to ?1?. l must be driven low, v il, dur- ing all asynchronous page read operations. in asynchronous page read mode, a page of data is internally read. each memory page con- sists of 16 words, and has the same set of values on a4-a21; only of a0 to a3 differ. the first read operation within the page has the normal access time (t avqv ), subsequent reads within the same page have much shorter access times (t avqv1 ). if the page changes then the normal, longer timings apply again. during asynchronous page read mode, the k in- put must be held low, v il . e must be kept low, v il upon completion of an asynchronous page read operation. the wait signal remains active until valid data is output from the device. see figure 17. and table 15. for details of the asynchronous page read timing requirements. synchronous burst mode burst mode allows high-speed synchronous read and write operations. in synchronous burst mode, the data is input or output to or from the memory array in bursts that are synchronized with the clock. after e goes low, the data address is latched on the first rising edge of the clock, k. during this first clock rising edge, the w signal indicates whether the operation is go- ing to be a read (w =v ih , figure 4. ) or write (w =v il , figure 5. ). in synchronous burst mode, the number of words to be input or output during a synchronous burst operation can be configured in the bus configura- tion register, bcr, as fixed length (4 words, 8 words or 16 words) or continuous. in synchro- nous continuous burst mode, the entire memory can be accessed sequentially in one burst opera- tion. the latency counter, stored in the bcr11 to bcr13 bits of the bcr register, defines how many clock cycles elapse before the first data value is transferred between the processor and the M69KB096AA. the wait output will be asserted as soon as a synchronous burst operation is initiated and will be deasserted to indicate when data is to be trans- ferred into (or out of) the memory array. the wait signal is also asserted when a continuous burst read or write operation crosses a row boundary. the wait assertion allows time for the new row to
9/48 M69KB096AA be accessed. it also allows any pending refresh operations to be performed (see figure 22., continuous burst read showing an output delay for end-of-row condition (bcr8=0,1) ). the processor can access other devices without being submitted to the initial burst latency by sus- pending the burst operation. burst operations can be suspended by halting the clock signal, holding it high or low. if another device needs to use the data bus while burst operations are suspended, the output enable signal, g , should be driven high, v ih , to disable data outputs; otherwise, g can remain low, v il . the wait output will remain asserted to prevent any other devices from using the processor wait line. burst operations can be resumed by taking g low, v il , and then restarting the clock as soon as valid data are available on the bus (see figure 21., synchronous burst read suspend and re- sume waveforms ). mixed mode when the bcr register is configured for synchro- nous operation, the device can support a combina- tion of synchronous burst read and asynchronous random write operations. the asynchronous random write operation re- quires that the clock signal remains low, v il , dur- ing the entire sequence. the l signal can either be used to latch the target address or remain low, v il , during the entire write operation. e must re- turn low, v il , during asynchronous and burst op- erations. note that the time, necessary to assure adequate refresh, is the same value as that for asynchronous read and write mode. mixed-mode operation greatly simplifies the inter- facing with traditional burst-mode flash memory controllers. low-power modes standby mode. during standby, the device cur- rent consumption is reduced to the level neces- sary to perform the memory array refresh operation. standby operation occurs when e is high, v ih , and no transaction is in progress. the device will enter standby mode when a read or write operation is completed, or when the ad- dress and control inputs remain stable for an ex- tended period of time. this ?active? standby mode will continue until address or control inputs change. temperature compensated refresh. the temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the device operating temperature. the leakage current of dram capacitive storage elements increases with the temperature. psram devices, based on a dram architecture, conse- quently require increasingly frequent refresh oper- ations to maintain data integrity as the temperature increases. at lower temperatures, the refresh rate can be decreased to minimize the standby current. the tcr mechanism allows adequate refresh rates to be set at four different temperature thresh- olds. these are defined by setting the rcr5 and rcr6 bits of the refresh configuration register, rcr. to minimize the self refresh current con- sumption, the selected setting must be higher than the operating temperature of the psram device. as an example, if the operating temperature is +50c, the +70c setting must be selected; the +15c and +45c settings would result in inade- quate refreshing and could cause data corruption. see table 9. for the definition of the refresh con- figuration register bits. partial array refresh. the partial array refresh (par) performs a limited refresh of part of the psram array. this mechanism enables the de- vice to reduce the standby current by refreshing only the part of the memory array that contains es- sential data. different refresh options can be de- fined by setting the rcr0 to rcr2 bits of the rcr register: full array one half of the array one quarter of the array one eighth of the array none of the array. these memory areas can be located either at the top or bottom of the memory array. the wait signal is used for arbitration when a read/write operation is launched while an on-chip refresh is in progress. if locations are addressed while they are undergoing refresh, the wait signal will be asserted for additional clock cycles, until the refresh has completed (see figure 6. and fig- ure 7. , collision between refresh and read or write operations). when the refresh operation is completed, the read or write operation will be al- lowed to continue normally.
M69KB096AA 10/48 deep power-down mode. deep power-down (dpd) mode is used by the system memory con- troller to de-activate the psram device when its storage capabilities are not needed. all refresh-re- lated operations are then disabled. when the deep power-down mode is enabled, the data stored in the device become corrupted. when re- fresh operations have been re-enabled, the device will be available for normal operations after t vchel (time to perform an initialization sequence). during this delay, the current consumption will be higher than the specified standby levels, but considerably lower than the active current. figure 4. synchronous burst read mode note: non-default bcr register settings: 3 clock cycle latency; wait active low; hold data one clock; wait asserted during delay . a0-a21 wait dq0-dq15 latency code 2 (3 clocks) k burst read identified (w = high) address valid ai06774b adv e g w hi z hi z lb/ub dq0 dq1 dq2 dq3
11/48 M69KB096AA figure 5. synchronous burst write mode (4-word burst) note: non-default bcr register settings: 3 clock cycle latency; wait active low; hold data one clock; wait asserted during delay . figure 6. collision between refresh and read operation note: additional wait states inserted to allow refresh completion. non-default bcr register settings: 3 clock cycle latency; wait active low; hold data one clock; wait asserted during delay. a0-a21 wait dq0-dq15 k additional wait states inserted to allow refresh completion address valid ai06776c l e g w hi z hi z lb/ub dq0 dq1 dq2 dq3 a0-a21 wait dq0-dq15 k additional wait states inserted to allow refresh completion address valid ai06776b l e g w hi z hi z lb/ub dq0 dq1 dq2 dq3
M69KB096AA 12/48 figure 7. collision between refresh and write operation note: additional wait states inserted to allow refresh completion. non-default bcr register settings: 3 clock cycle latency; wait active low; hold data one clock; wait asserted during delay. a0-a21 wait dq0-dq15 k additional wait states inserted to allow refresh completion address valid ai06777 e g w hi z hi z lb/ub dq0 dq1 dq2 dq3 l
13/48 M69KB096AA configuration registers two write-only user-accessible configuration reg- isters have been included to define device opera- tion. these registers are automatically loaded with default settings during power-up, and can be up- dated any time the device is operating in a standby state. the configuration registers (bcr and rcr) can be programmed and read using two methods: the cr controlled method (or hardware method) the software method. programming and reading the configuration registers using the cr controlled method the bcr and the rcr can be programmed and read using either a synchronous or an asynchro- nous write and read operation with the configu- ration register enable input, cr, at v ih . address bit a19 selects the register to be programmed or read (see table 4., register selection ). the val- ues placed on address lines a0 to a21 are latched into the register on the rising edge of l , e , or w , whichever occurs first. lb and ub are ?don?t care?. when cr is at v il , a read or write operation will access the memory array. see figures 27 and 33 , configuration register write in asynchronous and synchronous modes. table 4. register selection programming and reading the configuration registers by the software method each register can be read by issuing a read con- figuration register sequence (see figure 9., read configuration register (software method) , and programmed by issuing a set configuration reg- ister sequence (see figure 8., set configuration register (software method) . both sequences must be issued in asynchronous mode. the timings will be identical to those described in table 15., asynchronous read ac characteris- tics . the chip enable input, cr, is ?don?t care?. read configuration register and set configura- tion register sequences both require 4 cycles: 2 bus read and one bus write cycles to a unique address location, 3fffffh, indicate that the next operation will read or write to a configuration register. the data written during the third cycle must be ?0000h? to access the rcr and ?0001h? to access the bcr during the next cycle. the fourth cycle reads from or writes to the configuration register. register read or write operation a19 rcr read/write 0 bcr read/write 1
M69KB096AA 14/48 figure 8. set configuration register (software method) note: 1. only the bus configuration regi ster (bcr) and the refresh configuration register (rcr) can be modified. 2. to program the bcr or the rcr on last bus write cycle, dq0-dq15 must be set to ?0001h? and ?000h? respectively. 3. the highest order address location is not modified during this operation. 4. the third write operation must be controlled by the chip enable signal. figure 9. read configuration register (software method) note: 1. to read the bcr, rcr on last bus read cycle, dq0-dq15 must be set to ?0001h?, ?000h? respectively. 2. the highest order address location is not modified during this operation. 3. the chip enable signal, e , must be held high for 150ns before reading the content of the configuration register. 4. the third write operation must be controlled by the chip enable signal. addr. 3fffffh e g w lb, ub ai10600b 3fffffh 3fffffh 3fffffh dq0-dq15 (2) cr data in tehel2 tehel2 tehel2 don't care don't care (4) addr. 3fffffh e g w lb, ub ai10601b 3fffffh 3fffffh 3fffffh dq0-dq15 (1) cr data out tehel2 tehel2 tehel2 don't care don't care (3)
15/48 M69KB096AA bus configuration register the bus configuration register (bcr) defines how the psram interacts with the system memory bus. overall, it is identical to its counterpart on burst mode flash devices. at power-up, bcr is initialized to 9d4fh. refer to table 5. for the description of the bus configuration register bits. operating mode bit (bcr15). the operating mode bit allows the synchronous burst mode or the asynchronous mode (default setting) to be se- lected. latency counter bits (bcr13-bcr11). the latency counter bits are used to set the number of clock cycles between the beginning of a read or write operation and the first data becoming avail- able. for correct operation, the number of clock cycles can only be equal to 3 or 4 (default settings) and the latency counter bits can only assume the values shown in table 5., bus configuration reg- ister definition . see also table 7., latency counter configuration , and figure 12., example of latency counter configuration ). wait polarity bit (bcr10). the wait polarity bit indicates whether the wait output signal is ac- tive high or low. as a consequence, it also deter- mines whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. by default, the wait output signal is active high. wait configuration bit (bcr8). the system memory controller uses the wait signal to control data transfer during synchronous burst read read and write operations. the wait configuration bit is used to determine when the transition of the wait output signal be- tween the asserted and the deasserted state oc- curs with respect to valid data available on the data bus. when the wait configuration bit is set to ?0?, data is valid or invalid on the first clock rising edge im- mediately after the wait signal transition to the deasserted or asserted state. when the wait configuration bit is set to ?1? (de- fault settings), the wait signal transition occurs one clock cycle prior to the data bus going valid or invalid. see figure 10., wait configuration example , and figure 11., example of wait configuration during synchronous burst operation . clock configuration bit (bcr6). the clock configuration bit is used to configure the activ- eedge of the clock signal, k, during synchronous burst read or write operations. when the clock configuration bit is set to ?1? (default setting), the rising edge of the clock is active. configuring the active clock edge to the falling edge (bcr6 set to ?0?) is not supported. all of the waveforms shown in this datasheet cor- respond to a clock signal active on the rising edge. driver strength bit (bcr5). the driver strength bit allows to set the output drive strength to adjust to different data bus loading. normal driver strength (full drive) and reduced driver strength (a quarter drive) are available. by default, outputs are configured at ?half drive? strength. burst wrap bit (bcr3). the burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or allowed to step across the boundary (no wrap). the burst wrap bit is used to select be- tween ?wrap? and ?no wrap?. if the burst wrap bit is set to ?1? (no wrap), the device outputs data se- quentially regardless of burst boundaries. when continuous burst operation is selected, the inter- nal address switches to 000000h if the read ad- dress passes the last address. by default, burst wrap is selected. see also table 6., burst type definition .
M69KB096AA 16/48 burst length bits (bcr2-bcr0). the burst length bits set the number of words to be output during a synchronous burst read operation. they can be set for 4 words, 8 words, 16 words or continuous burst (default settings), where all the words are read sequentially regardless of address boundaries. burst write operations are always performed using the continuous burst mode. table 5. bus configuration register definition note: all burst write operations are performed in synchronous continuous burst mode. address bits bus configuration register bit description value description a21-a20 - - must be set to ?0? reserved a19 - register select 0 refresh selected 1 bus configuration register selected a18-a16 - - must be set to ?0? reserved a15 bcr15 operating mode bit 0 synchronous burst mode 1 asynchronous mode (default) a14 - - must be set to ?0? reserved a13-a11 bcr13- bcr11 latency counter bits (lc) 010 lc = 2 (3 clock cycles) 011 lc= 3 (4 clock cycles) (default) other configurations reserved a10 bcr10 wait polarity bit 0 wait active low 1 wait active high (default) a9 - - must be set to ?0? reserved a8 bcr8 wait configuration bit 0 wait asserted during delay 1 wait asserted one clock cycle before delay (default) a7 - - must be set to ?0? reserved a6 bcr6 clock configuration bit 0 not supported 1 rising clock edge (default) a5 bcr5 driver strength bit 0 full drive (default) 1 1/4 drive a4 - - must be set to ?0? reserved a3 bcr3 burst wrap bit 0 wrap (default) 1 no wrap a2-a0 bcr2-bcr0 burst length bit 001 4 words 010 8 words 011 16 words 111 continuous burst (default)
17/48 M69KB096AA table 6. burst type definition table 7. latency counter configuration note: 1. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. mode start add 4 words (sequential) 8 words (sequential) 16 words (sequential) continuous burst wrap (bcr3=?0?) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12... 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13... ... ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21... no wrap (bcr3=?1?) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 7 7-8-9-10-11-12-13- 14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 ... ... 14 14-15-16-17-18-19...-23-24-25-26-27-28-29 15 15-16-17-18-19-20...-24-25-26-27-28-29-30 latency configuration code maximum input clock frequency unit access time 70ns maximum clock rate in burst mode 80mhz maximum clock rate in burst mode 66mhz 2 (3 clock cycles) 53 (18.75ns) 44 (22.7ns) (1) mhz 3 (4 clock cycles) 80 (12.5ns) 66 (15.2ns) mhz
M69KB096AA 18/48 figure 10. wait configuration example figure 11. example of wait configuration during synchronous burst operation figure 12. example of latency counter configuration ai06795 dq0-dq15 bcr8='0' data valid during current cycle k wait data[0] data[1] hi-z data[0] hi-z dq0-dq15 bcr8='1' data valid during next cycle ai06797 dq0-dq15 k wait bcr8='0' data valid during current cycle data[0] wait bcr8='1' data valid during next cycle hi-z data[1] data[2] data[3] data[4] ai08900 dq0-dq15 bcr13-bcr11='010' k a0-a21 l dq0-dq15 bcr13-bcr11='011' address valid valid output valid output valid output 3 clock cycle latency 4 clock cycle latency valid output valid output valid output valid output
19/48 M69KB096AA refresh configuration register the refresh configuration register (rcr) is used for two purposes: to define how the self refresh of the psram array is performed to enable page read operations. altering the self refresh parameters can dramati- cally reduce current consumption in standby mode. at power-up, rcr is initialized to 0070h. refer to table 9. for the description of the refresh configuration register bits. page mode operation bit (rcr7). the page mode operation bit determines whether the asyn- chronous page read mode is enabled. at power- up, the rcr7 bit is set to ?0?, and so the asynchro- nous page read mode is disabled. temperature compensated refresh bits (rcr6-rcr5). the temperature compensated refresh bits allow an adequate refresh rate to be selected at one of four different temperature thresholds: +15c, +45c, +70c, and +85c. the default setting is +85c. see the temperature compensated refresh section for more details. deep power-down bit (rcr4). the deep pow- er-down bit enables or disables all refresh-related operations. the deep power-down mode is en- abled when the rcr4 bit is set to ?0?, and remains enabled until this bit is set to ?1?. at power-up, the deep power-down mode is disabled. see the deep power-down section for more de- tails. partial array refresh bits (rcr2-rcr0). the partial array refresh bits allow refresh operations to be restricted to a portion of the total psram ar- ray. the refresh options can be full array, one eighth, one quarter, one half, or none of the array. these memory areas can be located either at the top or bottom of the memory array. by default, the full memory array is refreshed (see table 8., address patterns for partial array refresh ). table 8. address patterns for partial array refresh note: rcr4 is set to ?1?. rcr2 rcr1 rcr0 refreshed area address space size of refreshe d area density 0 0 0 full array (default) 000000h-3fffffh 4 mbitsx16 64 mbits 0 0 1 bottom half of the array 000000h-1fffffh 2 mbitsx16 32 mbits 0 1 0 bottom first quarter of the array 000000h-0fffffh 1 mbitsx16 16 mbits 0 1 1 bottom first eighth of the array 000000h-07ffffh 512kbitsx 16 8 mbits 1 0 0 none of the array 0 0 0 1 0 1 top half of the array 200000h-3fffffh 2 mbitsx16 32 mbits 1 1 0 top quarter of the array 300000h-3fffffh 1 mbitsx16 16 mbits 1 1 1 top one-eighth of the array 380000h-3fffffh 512kbitsx 16 8 mbits
M69KB096AA 20/48 table 9. refresh configur ation register definition address bits bus configuration register bit description value description a21-a20 - - must be set to ?0? reserved a19 - register select 0 refresh selected 1 bus configuration register selected a18-a8 - - must be set to ?0? reserved a7 rcr7 page mode operation bit 0 page read mode disabled (default) 1 page read mode enabled a6-a5 rcr6-rcr5 temperature compensated refresh bits 11 +85c (default) 00 +70c 01 +45c 10 +15c a4 rcr4 deep power- down bit 0 deep power-down enabled 1 deep power-down disabled (default) a3 - - must be set to ?0? reserved a2-a0 rcr2-rcr0 partial array refresh bits 000 see table 8., address patterns for partial array refresh 001 010 011 100 101 110 111
21/48 M69KB096AA maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 10. absolute maximum ratings note: 1. whichever is the lower. symbol parameter min max unit t a ambient operating temperature ?30 85 c t stg storage temperature ?55 150 c v cc core supply voltage ?0.2 2.45 v v ccq input/output buffer supply voltage ?0.2 4.0 v v io input or output voltage ?0.5 4.0 or v ccq +0.3 (1) v
M69KB096AA 22/48 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 11., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 11. operating and ac measurement conditions note: 1. all voltages are referenced to v ss . figure 13. ac measurement i/o waveform figure 14. ac measurement load circuit note: 1. logic states ?1? and ?0? correspond to ac test inputs dr iven at vccq and vss respectively. input timings begin at vccq/2 and output timings end at vccq/2. input rise and fall time (10% to 90%) are lower than 1.6ns. 2. all the tests are performed with the outputs configured as full drive strength (bcr[5]=0). parameter M69KB096AA unit min max v cc supply voltage 1.7 1.95 v v ccq input/output buffer supply voltage 1.7 3.3 v ambient operating temperature ? 30 85 c load capacitance (c l ) 30 pf output circuit protection resistance (r 1, r 2 ) v ccq = 1.8v 2.7 k ? v ccq = 2.5v 3.7 k ? v ccq = 3.0v 4.5 k ? input pulse voltages 0 v cc v input and output timing ref. voltages v cc /2 v output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc v input rise and fall time (t ) 1.6 ns ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai07222d v ccq out device under test c l r 1 r 2
23/48 M69KB096AA table 12. capacitance note: 1. these parameters are not fully tested. table 13. dc characteristics note: 1. this parameter is specified with the outputs disabled to av oid external loading effects. the user must add the current r equired to drive the output capacitance expected in the actual system. 2. i sb (max) values are measured with rcr2 to rcr0 bi ts set to ?000? (full array refresh) a nd rcr6 to rcr5 bits set to ?11? (temper- ature compensated refresh threshold at +85c). in order to achieve low standby current, all inputs must be driven either to v ccq or v ss . isb may be slightly higher for up to 500 ms after power-up or when entering standby mode. 3. the operating temperature is +25c. symbol parameter test condition min max unit c in1 address input capacitance v in = 0v 6pf c io data input/output capacitance v io = 0v 6pf symbol parameter test condition min. typ max. unit i cc1 (1) operating current: asynchronous random read/write v in =v ih or v il , e = v il , i out = 0ma 70ns 25 ma 85ns 20 ma i cc1p (1) operating current: asynchronous page read 70ns 15 ma 85ns 12 ma i cc2 (1) operating current: initial access, burst read/write 80mhz 35 ma 66mhz 30 ma i cc3r (1) operating current: continuous burst read 80mhz 18 ma 66mhz 15 ma i cc3w (1) operating current: continuous burst write 80mhz 35 ma 66mhz 30 ma i sb (2) v cc standby current v in = v ccq or 0v, e = v ih 120 a i li input leakage current 0v v in v cc 1a i lo output leakage current g = v ih or e = v ih 1a i zz (3) deep-power down current v in = v ih or v il 10 a v ih input high voltage 1.4 v ccq + 0.2 v v il input low voltage ? 0.2 0.4 v v oh output high voltage i oh = ? 0.2ma 0.8v ccq v v ol output low voltage i ol = 0.2ma 0.2v ccq v
M69KB096AA 24/48 table 14. par and tcsr specifications and conditions note: 1. in order to achieve low standby current, all inputs must be driven to either vccq or vss. isb may be slightly higher for up to 500 ms after power-up or when entering standby mode. 2. rcr values for 85c are 100 percent tested. tcr values for 15c, 45c and 70c are sampled only. figure 15. asynchronous random read ac waveforms symbol parameter test condition refreshed memory areas maximum operating temperature (2) unit +15c rcr[6-5]=10 +45c rcr[6-5]=01 +70c rcr[6-5]=00 +85c rcr[6-5]=11 i sb (1) maximum standby current in tcsr and par modes v in = v ih or v il , e = v ih full 70 85 105 120 a 1/2 65 80 100 115 1/4 60 75 95 110 1/8 57 70 90 105 050556070 ai06780b a0-a21 wait valid address tehel tehqz tblqv hi-z hi-z tavax telqv tghqx tbhqz tghqz tglqv teltv valid output hi-z telqx tglqx e lb/ub g w dq0-dq15 tavqv hi-z tblqx l tehtz
25/48 M69KB096AA figure 16. l controlled asynchronous random read ac waveforms ai06781b a0-a21 wait valid address tehel tehqz tblqv hi-z hi-z telqv tghqx tbhqz tghqz tglqv teltv valid output hi-z telqx tglqx l e lb/ub g w dq0-dq15 tavqv hi-z tblqx tlhll tavlh tlhax tllqv tlllh tellh tehtz
M69KB096AA 26/48 figure 17. asynchronous page read ac waveforms ai06782b a4-a21 wait valid address tehel tehqz tblqv hi-z hi-z tavax telqv tghqx tbhqz tghqz tglqv teltv hi-z telqx tglqx e lb/ub g w dq0-dq15 tavqv hi-z tblqx a1-a3 valid address valid valid tavav valid output valid output valid output valid output tehel tavqv1 tavqx valid l tehtz
27/48 M69KB096AA table 15. asynchronous read ac characteristics note: 1. all the tests are performed with the outputs configured in ?full drive? strength (bcr5=?0?). 2. the timing is related to asynchronous page mode only. 3. these timings have been obtained with th e ac measurement load circuit shown on figure 14. . the transition timings measure a transition of 100mv between the high-z level (v ccq /2) and v oh or v ol . 4. these timings have been obtained with the ac measurement load circuit shown on figure 14. . the high-z timings measure a transition of 100mv between v oh or v ol and v ccq /2. symbol alt. parameter M69KB096AA unit 70ns 85ns min max min max t avqv t aa address valid to output valid 70 85 ns t llqv t aadv l low to output valid 70 85 ns t avqv1 t apa page access time 20 25 ns t lhax t avh l high to address transition 5 5 t avlh t avs address valid to l high 10 10 t blqv t ba upper/lower byte enable low to output valid 70 85 ns t bhqz (4) t bhz upper/lower byte enable high to output hi- z 88ns t blqx (3) t blz upper/lower byte enable low to output transition 10 10 ns t ehel t cbph chip enable high between subsequent mixed-mode read operations 55ns t eleh (2) t cem maximum chip enable pulse width 8 8 s t eltv t cew chip enable low to wait valid 1 7.5 1 7.5 ns t ehtz chip enable high to wait high-z 8 8 ns t elqv t co chip enable low to output valid (chip select access time) 70 85 ns t ellh t cvs chip enable low to l high 10 10 ns t ehqz (4) t hz chip enable high to output hi-z 8 8 ns t elqx (3) t lz chip enable low to output transition 10 10 ns t glqv t oe output enable low to output valid 20 20 ns t ghqx t oh output enable high to output transition 5 5 ns t avqx t oha data hold from address change 5 5 ns t ghqz (4) t ohz output enable high to output hi-z 8 8 ns t glqx (3) t olz output enable low to output transition 5 5 ns t avav t pc page cycle time 20 25 t avax t rc read cycle time 70 85 ns t lllh t vp l pulse width low 10 10 ns t lhll t vph l pulse width high 10 10 ns
M69KB096AA 28/48 figure 18. single access synchronous burst read ac waveforms note: 1. non default bcr register settings: 3 clock cycle latency; wait active low; wait asserted during delay. 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. a0-a21 dq0-dq15 k address valid ai06783 l e g wait hi z hi z lb/ub valid output hi-z hi-z burst read identified tkhkh tkhkl tavkh tkhax tavlh tllkh telkh tkhqv1 tkheh tehqz tglqv tghqz w twhkh tkhwx tglqx tblkh tkhbx teltv tkhtv tkhqv2 tkhqx2 (w = high) tkhlh
29/48 M69KB096AA figure 19. synchronous burst read (4-word) ac waveforms note: 1. non default bcr register settings: 3 clock cycle latency; wait active low; wait asserted during delay. 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. a0-a21 wait d0-d15 k tavkh tkhkh tkhax tkhqv1 valid address tkhqx2 tehqz tkheh tllkh tglqx tehel telkh twhkh tkhwx tblkh tkhbx tghqz tavlh tkhkl read burst identified tkhtx hi-z valid output valid output valid output valid output hi-z hi-z tglqv ai06784 e g w lb/ub (w = high) teltv tkhqz l tkhlh
M69KB096AA 30/48 figure 20. lb /ub controlled, synchronous burst read (4-word) ac waveforms note: 1. non default bcr register settings: 3 clock cycle latency; wait active low; wait asserted during delay. 2. the burst length bits bcr0 to br2 are set to ?001? (4 words). 3. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. a0-a21 wait dq0-dq15 k tavkh tkhkh tkhax tkhqv1 valid address tkhqx2 tehqz tkheh tllkh tglqx tehel telkh twhkh tkhwx tblkh tkhbx tghqz tavlh tkhkl read burst identified tkhtx hi-z valid output valid output valid output hi-z hi-z tglqv ai06785 e g w lb/ub (w = high) teltv tkhqz hi-z tkhqz tkhqx1 tkhqz l tkhlh
31/48 M69KB096AA figure 21. synchronous burst read suspend and resume waveforms note: 1. non default bcr register settings: 3 clock cycle latency; wait active low; wait asserted during delay. 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. 0 -a21 w ait 0 -d15 tavkh tklkl tkhax tkhqx2 tehqz tllkh tglqx tehel telkh twhkh tkhwx tblkh tkhbx tghqz tavlh tkhkl hi-z valid output hi-z hi-z ai08760c w b /ub tkhqv1 l valid output valid address valid address tglqv tghqz valid output valid output valid output valid output tkhlh tllkh tk h tglqx tglqv
M69KB096AA 32/48 figure 22. continuous burst read showing an output delay for end-of-row condition (bcr8=0,1) note: 1. non default bcr register settings: 3 clock cycle latency; wait active low, wait asserted during delay; burst wrap bit bc r3 set to ?0? (wrap). 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. 3. wait will be asserted for a maximum of 2xlc cycles (lc being the latency code set through bcr[13-11]). 4. e must not remain low longer that t eleh . tkhqv2 tkhqx2 a0-a21 dq0-dq15 k tkhtv tkhkh tklkh tf wait wait configigured with bcr8 = '1' wait configigured with bcr8 = '0' valid output valid output valid output valid output ai06787b e g lb/ub w don't care don't care don't care don't care tkhtx l (3) (4)
33/48 M69KB096AA table 16. synchronous burst read ac characteristics note: 1. all the tests are performed with the outputs configured in ?full drive? strength (bcr5=?0?). 2. these timings have been obtained with the ac measurement load circuit shown on figure 14. . the high-z timings measure a transition of 100mv between v oh or v ol and v ccq /2. 3. these timings have been obtained with th e ac measurement load circuit shown on figure 14. . the transition timings measure a transition of 100mv between the high-z level (v ccq /2) and v oh or v ol . 4. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. 5. when configured in synchronous mode (bcr15 = 0) , a refresh opportunity must be provided every t eleh . a refresh opportunity is satisfied by either of the following two conditions: e = v ih during clock input k rising edge or e = v ih for longer than 15ns. symbol alt. parameter M69KB096AA unit 80mhz 66mhz min max min max t khqv1 t aba burst access time 46.5 56 ns t khqv2 t aclk delay from clock high to output valid 9 11 ns t avlh t avs address valid to l high 10 10 ns t glqv t boe delay from output enable low to output valid in burst mode 20 20 ns t ehel (5) t cbph chip enable high between subsequent mixed-mode read operations 55ns t eltv t cew chip enable low to wait valid 1 7.5 1 7.5 ns t eleh (5) t cem maximum chip enable low pulse 8 8 ns t khkh (4) t clk clock period 12.5 20 15 20 ns t elkh t csp chip enable low to clock high 4.5 20 5 20 ns t khax t khbx t khwx t kheh t khlh t hd hold time from active clock edge 2 2 ns t ehqz (2) t hz chip enable high to output hi-z 8 8 ns t r t f t khkl clock rise time clock fall time 1.8 2.0 ns t khtv t khtx t khtl clock high to wait valid clock high to wait transition 911ns t khqz t khz clock high to output hi-z 3 8 3 8 ns t khqx1 t klz clock high to output transition 2 5 2 5 ns t khqx2 t koh output hold from clock high 2 2 ns t khkl t klkh t kp clock high to clock low clock low to clock high 45ns t ghqz (2) t ohz output enable high to output hi-z 8 8 ns t glqx (3) t olz output enable low to output transition 5 5 ns t avkh t llkh t blkh t whkh t chkh t sp set-up time to active clock edge 3 3 ns
M69KB096AA 34/48 figure 23. chip enable controlled, asynchronous write ac waveforms figure 24. lb /ub controlled, asynchronous write ac waveforms dq0-dq15 valid address hi-z hi-z tavax teltv valid input tavwh twhax teleh, telwh tdveh tblbh hi-z tehdx twlwh twhwl ai06788c a0-a21 g wait lb/ub w l e tavel tehtz dq0-dq15 valid address hi-z hi-z tavax teltv valid input tavwh twhax teleh, telwh tdveh tblbh hi-z tehdx twlwh twhwl ai06789d a0-a21 g wait lb/ub w l e tbhtz
35/48 M69KB096AA figure 25. write enable controlled, asynchronous write ac waveforms dq0-dq15 valid address hi-z hi-z tavax teltv valid input tavwh twhax teleh, telwh tdveh tblbh hi-z tehdx twlwh twhwl ai06790c a0-a21 g wait lb/ub w l e twhtz tavwl
M69KB096AA 36/48 figure 26. l controlled, asynchronous write ac waveforms dq0-dq15 valid address hi-z hi-z tavlh teltv valid input tlhax tllwh teleh, telwh tdveh tblbh hi-z tehdx twlwh twhwl ai06791c a0-a21 g wait lb/ub w l e tlhll tlllh tavwh twhtz
37/48 M69KB096AA figure 27. configuration register write in asynchronous mode followed by read operation note: 1. non default bcr register settings: latency code two (three clocks); wait active low; hold data one clock; wait asserted during delay. 2. a19 = v il to load rcr; a19 = v ih to load bcr. a0-a21 except a19 k opcode address address a19 initiate control register access cr tavlh tllvh tlhll tehel telwh select control register l e g w ai06778 data valid dq0-dq15 lb/ub tavlh write address bus value to control register twlwh
M69KB096AA 38/48 figure 28. asynchronous write followed by synchronous burst read (4-word) ac waveforms note: 1. non default bcr register settings: 3 clock cycle latency; wait active low; wait asserted during delay. 2. when configured in synchronous mode (bcr15 = 0) , a refresh opportunity must be provided every t eleh . a refresh opportunity is satisfied by either of the following two conditions: e = v ih during clock input k rising edge or e = v ih for longer than 15ns. 3. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. a0-a21 wait d0-d15 k tavkh tkhkh tkhax tkhqv1 valid address tkhqx2 tllkh telkh twhkh tkhwx tblkh tkhbx tghqz tkhkl tglqv valid output valid output valid output hi-z ai11317 e g w lb/ub teltv tkhqz l tkhlh tavax tlhll twhdx hi-z tavwl tavax valid output valid output valid output valid address valid address tlhax tavlh twhax tavwh tlllh tllwh telwh tehel (2) tllwl twlwh twhwl tbllh tblwh twldv tdvwh
39/48 M69KB096AA figure 29. synchronous burst read (4-word) followed by asynchronous write ac waveforms note: 1. when configured in synchronous mode (bcr15 = 0), a refresh opportunity must be provided every t eleh . a refresh opportunity is satisfied by either of the following two conditions: e = v ih during clock input k rising edge or e = v ih for longer than 15ns. a0-a21 dq0-dq15 k address valid ai11318 l e g wait hi z lb/ub valid output hi-z burst read identified tkhkh tavkh tkhax tllkh telkh tkhqv1 tkheh tehqz tglqv tghqz w twhkh tkhwx tglqx tblkh tkhbx teltv tkhtv tkhqv2 tkhqx2 (w = high) tkhlh valid address hi-z teltv valid input tavlh tlhax teleh, telwh tdveh tblbh tehdx twlwh tavwl tlhll tlllh tllwh telwl tehel (1) twhwl twhtz
M69KB096AA 40/48 table 17. asynchronous write ac characteristics symbol alt. parameter M69KB096AA unit 70ns 85ns min max min max t avel t avwl t avbl t llwl t elwl t as address setting time 0 0 s t lhax t avh l high to address transition 5 5 ns t avlh t avs address valid to l high 10 10 ns t avwh t avbh t aw address valid to write enable high address valid to upper/lower byte enable transition 70 85 ns t blbh t bleh t blwh t bw upper/lower byte enable low to end of write operation 70 85 ns t eltv t cew chip enable low to wait valid 1 7.5 1 7.5 ns t axch t cka in mixed-mode operation: delay between address transition in asynchronous write mode and clock high in burst read mode 70 85 ns t ehel t cph chip enable high between subsequent asynchronous operations 55ns t ellh t bllh t cvs chip enable low to l high 10 10 ns t elbh t elwh t cw chip enable low to end of write operation 70 85 ns t ehdx t whdx t bhdx t dh input hold from end of write operation 0 0 ns t dveh t dvbh t dvwh t dw data to write time overlap 23 23 ns t lllh t vp l pulse width low 10 10 ns t lhll t vph l pulse width high 10 10 ns t llwh t vs l low to write enable high 70 85 ns t avax t whwh t wc write cycle time 70 85 ns t wlbh t wleh t wlwh t wp write pulse width 46 55 ns t whwl t wph write enable pulse width high 10 10 ns t whax t wr write enable high to address transition 0 0 ns t wldv t whz write enable low to data valid 8 8 ns
41/48 M69KB096AA note: 1. we# low time must be limited to t cem (8 s). 2. these timings have been obtained with t he ac measurement load circuit shown on figure 14. the transition timings measure a transition of 100 mv between the high-z level (v ccq/2 ) and v oh or v ol . 3. these timings have been obtained with the ac measurement load circuit shown on figure 14. the high-z timings measure a tran- sition of 100 mv between v oh or v ol and v ccq/2 . figure 30. synchronous burst write ac waveform note: 1. non default bcr register settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. t ehtz t bhtz t whtz t hz chip enable high to wait hi-z lb /ub high to wait hi-z write enable high to wait hi-z 88ns symbol alt. parameter M69KB096AA unit 70ns 85ns min max min max t avel t avwl t avbl t llwl t elwl t as address setting time 0 0 s t lhax t avh l high to address transition 5 5 ns a0-a21 wait d0-d15 k tkhkh valid address tkhdx telkh twhkh tkhwh tavkh write burst identified tkhtv hi-z valid input hi-z hi-z ai06792b e g w (w = low) tkheh tehel tblkh tkhbh lb/ub teltv tdvkh l valid input valid input valid input teleh tllkh tkhlh
M69KB096AA 42/48 figure 31. continuous burst write showing an output delay for end-of-r ow condition (bcr8=0) note: 1. non default bcr register settings: 3 clock cycle latency; wait active low, burst wrap bit bcr3 set to ?0? (wrap). 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. 3. wait will be asserted for a maximum of (2xlc)+1 cycles (lc being the latency code set through bcr[13-11]) 4. taking e high or l low will abort the burst operation and the writing of the first data. a0-a21 dq0-dq15 k tkhtv tkhkh tklkh tf wait ai06793b e g lb/ub w don't care don't care don't care don't care tkhtx l tkhdx tdvkh valid input d[n] valid input d[n+1] end of row valid input d[n+3] valid input d[n+2] (3) valid input d[n+4]
43/48 M69KB096AA figure 32. synchronous burst write followed by read ac waveforms (4 words) note: 1. the latency type can set to fixed or variable mode. the latency is set to 3 clock cycles (bcr13-bcr11 = 101). the wait s ignal is active low (bcr10=0), and is asserted during delay (bcr8=0). in fixed latency mode, row boundary crossing 2. e can remain low between the burst read and burst write operation, but it must not be held low for longer than t eleh . addr. wait dq0- dq15 k tkhax ai11313 e g w l tkhkh d in0 d in1 d in2 d in3 ub, lb tklkh tkhkl tavkh tkhlh tllkh telkh twlkh tkhwh tdvkh tkhll tehel tghqz tglqx tkhqx2 d o0 d o1 d o2 d o3 tkhdx tkhax tavkh (2) tkheh telkh tkhlh tkheh tkhtx tkhtx twhkh tkhwl
M69KB096AA 44/48 figure 33. configuration register write in synchronous mode followed by read operation note: 1. non default bcr register settings: latency code two (three clocks); wait active low; hold data one clock; wait asserted during delay. 2. a19 = v il to load rcr; a19 = v ih to load bcr. latch control register address hi-z opcode address address hi-z latch control register value ai06779b a0-a21 except a19 k a19 cr e g w dq0-dq15 lb/ub tavkh l wait tchkh tkhlh telkh tehel twlkh tkhlh teltv trhkh tkhrl
45/48 M69KB096AA table 18. synchronous burst write ac characteristics note: 1. when configured in synchronous mode (bcr15 = 0), a refresh opportunity must be provided every t eleh . a refresh opportunity is satisfied by either of the following two conditions: e = v ih during clock input k rising edge or e = v ih for longer than 15ns. 2. clock rates lower than 50mhz (clock period higher than 20ns) are allowed as long as t elkh specifications are met. figure 34. power-up ac waveforms table 19. power-up ac characteristics symbol alt. parameter M69KB096AA unit 80mhz 66mhz min max min max t ehel (1) t cbph chip enable high between subsequent mixed-mode read operations 55ns t eltv t cew chip enable low to wait valid 1 7.5 1 7.5 ns t khkh (2) t clk clock period 12.5 20 15 20 ns t elkh t csp chip enable low to clock high 4.5 20 5 20 ns t khax t khbh t khwh t kheh t khlh t khrl t hd hold time from active clock edge 2 2 ns t r t f t khkl clock rise time clock fall time 1.8 2.0 ns t khtv t khtl clock high to wait valid 9 11 ns t khkl t kp clock high to clock low 4 5 ns t avkh t blkh t whkh t wlkh t chkh t rhkh t sp set-up time to active clock edge 33ns t eleh (1) t cem maximum chip enable pulse width 8 8 s symbol alt. parameter M69KB096AA unit 70ns 85ns min max min max t vchel t pu initialization delay 150 150 s ai06794 vcc, vccq tvchel 1.7v device ready for normal operation device initialization e
M69KB096AA 46/48 part numbering table 20. ordering information scheme the notation used for the device number is as shown in table 20. . not all combinations are necessarily available. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmicroelectronics sales office. example: m69kb096 a a 70 c w 8 device type m69 = psram mode k =tested die operating voltage b = v cc = 1.7 to 1.95v, burst, address/data bus standard x16 array organization 096 = 64 mbit (4mb x16) option a = 1 chip enable die revision a = revision a speed class 70 = 70ns 85 = 85ns maximum clock frequency a= 66 mhz max clock frequency in burst read mode c= 80mhz max clock frequency in burst read mode package w = unsawn wafer operating temperature 8 = ?30 to 85 c
47/48 M69KB096AA revision history table 21. document revision history date rev. revision details 13-oct-2004 0.1 first issue. 11-feb-2005 0.2 i sb current for standard leakage option added in features summary . i sb current for standard leakage option added in table 13., dc characteristics and test conditions updated. i tcr current for standard leakage option added in table 14., temperature compensated refresh specifications and conditions . i pa r current for standard leakage option added in table 15., partial array refresh specifications and conditions . standard leakage option added in table 20., ordering information scheme . 29-apr-2005 1.0 root part number changed to M69KB096AA. 104mhz maximum clock frequency and low leakage option removed. temperature range updated to ?30c to +85c. clock input (k). definition updated. figure 3., block diagram modified. bus modes tables 2 , 3 and synchronous burst mode paragraph updated. output impedance bit (bcr5) renamed driver strength and definition updated. r1 and r2 updated in table 13., dc characteristics and refresh specifications and conditions tables merged into table 14. . figures 15 , 16 , and 17 describing asynchronous read ac waveforms updated. figures 18 , 19 , 20 , 21 and 22 describing synchronous read ac waveforms updated. figures 23 , 24 , and 25 , describing asynchronous write ac waveforms updated. t avwl and t avbl added in table 17., asynchronous write ac characteristics . figures 28 and 29 added. figures 30 , 31 , and 32 , describing synchronous write ac waveforms updated. figure 32., synchronous burst write followed by read ac waveforms (4 words) added. t rhkh and t khrl added in table 18., synchronous burst write ac characteristics table 21., bond pad location and identification modified to express the pad coordinates from the center of the die. 16-june-2005 2.0 , features summary, operating modes and figure 5., synchronous burst write mode (4-word burst) modified. 18-aug-2005 3.0 updated note 2 in table 13., page 23 , added notes to table 14., page 24 and table 17., page 40 . deleted note 5 from table 15., page 27 . 12-dec-2005 4 clock rate added in datasheet title. test conditions for i cc1 , i cc1p , i cc2 , i cc3r , i cc3w and i sb updated in table 13., dc characteristics . 19-jan-2006 5 section wafer and die specifications removed.
M69KB096AA 48/48 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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